Quantum control, closer to the qubits.4 K / Cryo-CMOS
GQIG / QUANTUM DEALFLOW LIVE / IMEC, LEUVEN
Excellence Award.
Qifrost received the Quantum Innovation Excellence Award at GQIG’s Quantum Dealflow Live in Leuven. Control electronics at 4 K reduce wiring, thermal load and system complexity as qubit counts scale.
Qifrost won the Q2B Startup Pitch Competition in Copenhagen, run by the BioInnovation Institute and hosted by QC Ware. The jury spanned 55 North, Novo Holdings, Playground Global, QuNorth, Microsoft and QAI Ventures, with seven finalists from five countries.
Qifrost won the pitching competition at NAMIC Singapore’s Startup Innovation Forum 2026, earning a fast track to the SLINGSHOT 2026 Top 50 Finals at SWITCH this October.
Eric W. Cao represented Singapore at Quantum Meets 2026 in Amsterdam, discussing the research, partnerships and commercial ecosystem needed to build a quantum industry.
Qifrost complements qubit developers by owning the full design-to-packaging stack for cryo-control in a key semiconductor node of Southeast Asia. Design, cryogenic test, characterization and packaging in-house. Device fab outsourced at leading foundries.
QELVINTM is the control layer that breaks through the quantum wiring wall. It runs at 4K inside the cryostat, adjacent to the qubits: one chip quietly conducting thousands of them, so cabling scales as log(n) and the gold-wire tangle disappears. Validated silicon, already running in the cold.
Capabilities
Everything below the qubit layer
A full cryo-control stack: designed, taped out, packaged and validated in-house.
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WHERE IT LIVES IN THE STACK
300 K | room temp4 K | QELVIN~mK | qubits
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Built In-House
Under one roof
Design, cryogenic test, characterisation and packaging in-house. Only the wafer fab is outsourced.
Publications
Selected Research
Peer-reviewed work from our team and collaborators across cryogenic CMOS control and superconducting advanced packaging, published with IEEE.
Today's control architecture hits two physical walls. Both get worse with every qubit you add, and 1M+ qubit targets demand on-chip classical control.
QELVIN runs at 4 K inside the cryostat, adjacent to the qubits, so cabling scales as log(n).
Inside the cryostatToday: one line per control channel, from 300 K to ~mK
WALL 01
The Wiring Bottleneck
3 to 5coaxial cables per qubit, 300K to ~mK
4,000+cables at just 1,000 qubits
10xlatency reduction targeted at 4K
At that scale, the wiring is physically unscalable.
RT I/O round-trip latency runs in the tens of nanoseconds.
That is long enough to break the feedback loop quantum error correction needs.
At 1,000 qubits, conventional 1:1 wiring hits the wall.
Conventional wiring: one line per control channel
Cooling power at 4K is tiny, every milliwatt counts.
WALL 02
The 4K Power Budget
1 mW → ~1 Wcooling cost at 4K
~1,000×real-world overhead
~75×Carnot limit, 4K to 300K
The budget is ~1 mW / qubit.
Carrier freeze-out, mobility shift and threshold drift change every device.
Each block needs dedicated cryogenic characterisation.
Read moreRead less
Real cryocoolers run at only a fraction of ideal efficiency, so their cooling overhead exceeds the ideal thermodynamic (Carnot) limit. Every watt they draw at room temperature has to be wired in, powered, and dissipated somewhere, which is why the power budget for electronics living at 4K is so tight, and why every milliwatt of on-chip dissipation counts.
Standard CMOS models break at 4K, so silicon must be re-characterised and re-designed for the cold.
The Qifrost answer
Move control into the cold, directly closer to the qubits
QELVIN, Qifrost's cryo-CMOS control layer, replaces much of the room-temperature rack today. It interfaces with a TSV interposer, on Qifrost's roadmap, and a customer-provided qubit array bonded beneath, while on-chip sequencing distributes each control resource across many qubits.
1
QELVIN cryo-CMOS: control & readout ASICs at 4K, log(n) wiring
Control starts digital, at the computer. Today, room-temperature electronics turn it analog at the rack, and a thick bundle of lines runs the full 300 K-to-~mK span into the cryostat. Qifrost’s QELVIN converts to analog right at 4 K, next to the qubits, so only a handful of short lines remain.
Today
A thick bundle of lines runs the full 300 K‑to‑~mK span
More qubits means more analog lines running the full cryostat span, from the room-temperature rack down to the qubits.
Future of Quantum Computing
QELVIN cuts that down to a few short lines at 4 K
QELVIN converts to analog right next to the qubits, at 4 K, collapsing that bundle down to a handful of short lines.
Control electronics run at 300 K, about 300× hotter than the qubits at ~mK. Qifrost moves the digital-to-analog boundary to 4 K, adjacent to the qubit layer, cutting the number of lines that cross the full cryostat.
The scaling problem, visualised
Cables vs qubit count
Conventional control wiring grows linearly and hits a wall. On-chip sequencing keeps it flat.
Conventional (1:1 wiring)Qifrost QELVIN (log n)
Conventional
One cable bundle per qubit, all the way down
Qifrost QELVIN
Control silicon adjacent to qubits, far fewer lines in
QELVIN™ | CRYOGENIC CONTROL
See how QELVIN solves it
Explore the control platform, validated silicon and technical specifications.
Electronic components for qubit control and readout that operate in the cryogenic regime, adjacent to the qubit layer. One control resource addresses many qubits through on-chip sequencing, so wiring scales as log(n) rather than 1:1 with qubit count.
→Cryo-CMOS control & readout ASICs on FD-SOI, validated at 4K, 77K and room temperature
→TSV-type cryo packaging, CMOS-compatible, for adjacent-to-qubit integration
→Multiplexed sparse control: < 3dB insertion loss, 25 to 35 dB isolation, switching in nano seconds
→Platform-agnostic: superconducting, spin and photonic architectures
The cryogenic layer Qifrost owns grows with every generation, and control keeps moving closer to the qubits.
GENERATION 1PRE-2026
Control still lives at 300 K
Classical Compute (FPGA / ASIC) and Control / Readout both sit in the room-temperature rack.
Qubit Layer: superconducting & Si-spin, at ~mK: nothing cryogenic sits between the rack and the qubits yet.
~10² qubits
GENERATION 22027 to 2030
QELVIN takes over at 1 to 4 K
Classical Compute stays at 300 K.
DAC+DEMUX / MUX+ADC Control / Readout moves to the 1 to 4 K cryo stage.
Owned by Qifrost.
Qubit Layer: superconducting & Si-spin, at ~mK.
~10³ qubits
GENERATION 32030+
The cryo-interposer completes the stack
Classical Compute remains the only thing left at 300 K.
Control / Readout and the Cryo-interposer both run at 1 to 4 K.
The cryo-interposer sits directly between the QELVIN control chip and the qubit layer, both cooled to the same 4 K stage. Because it's a through-silicon-via (TSV), CMOS-compatible layer rather than off-chip wiring, it lets thousands of short, dense electrical connections replace long cable runs, cutting the parasitic capacitance and latency that degrade qubit control fidelity, while remaining manufacturable on standard semiconductor lines rather than built by hand.
Qubit Layer: superconducting & Si-spin, at ~mK.
~10⁶ qubits
BOTTOM LINEEvery generation pushes control closer to the qubits: the 4K layer is the only viable path to scaled quantum computers.
Architecture
Inside the control / readout layer
Conceptually a generic RF transceiver, with qubits instead of the antenna. The blocks between the room-temperature interface and the qubit array sit at 4 K: that's the layer Qifrost builds.
Beachhead: proven today
16-bit DAC / ADC core
1 to 2 GS/s
0.2 mW
60 dB SFDR
~20 mVrms output
< 1 DNL / INL
Fabricated on FD-SOI
START: the 16-bit DAC/ADC coreEND: the complete qubit interface
CONTROLDAC → filter → up-convert → driver → DEMUX
READOUTMUX → LNA → down-convert → filter → ADC
Digital control at the room-temperature interface drives the chain; the quantum processor sits at the far end. Both paths live at 4 K, adjacent to the qubits at ~mK.
BOTTOM LINEThe blocks between the room-temperature interface and the qubit array sit at 4 K: this is the layer Qifrost builds.
Why Qifrost
Two advantages
SG
01 | ORIGIN
The A*STAR | Singapore advantage
Spun out of the A*STAR Quantum Innovation Centre, with direct access to Singapore's mature semiconductor supply chain: fabs, packaging and talent. Cryo silicon built to be manufactured, not just demonstrated.
A*STAR spin-out
Singapore supply chain
Built to be manufactured
4K
02 | TECHNOLOGY
The cryo-CMOS advantage
Cryogenic CMOS brings conversion and sequencing into the cold stage, close to the quantum processor. Local multiplexing concentrates control across large qubit arrays, sharply reducing the cable count. CMOS-compatible packaging and validated silicon replace the cable spaghetti.
Diego Van Hemelryck launches The Cryo Dweller, a recurring roundup of research papers shaping cryogenic quantum hardware: one paper per card, from 6 K down to 70 mK, with links to the source papers.